Area-efficient high-throughput MAP decoder architectures.

Area-efficient high-throughput MAP decoder architectures.

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 13, 8 (2005).
Päätekijä: Seok-Jun Lee
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
BIP MAP decoder.
CMOS standard cell library.
MAP decoder architecture.
Block-interleaved pipelining.
Broadband communication system.
Computational kernel.
Iterative decoder.
Logic complexity.
Look-ahead computation.
Maximum a posteriori probability.
Parallel architecture.
Parallel processing.
Post-layout simulation.
Reduced memory complexity.
Symbol-based decoding.
Turbo decoder.
Turbo equalizer.