Area-efficient high-throughput MAP decoder architectures.

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is...

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Bibliographic Details
Published in:	IEEE Transactions on VLSI systems 13, 8 (2005).
Main Author:	Seok-Jun Lee
Format:	Article
Language:	English
Subjects:	BIP MAP decoder. CMOS standard cell library. MAP decoder architecture. Block-interleaved pipelining. Broadband communication system. Computational kernel. Iterative decoder. Logic complexity. Look-ahead computation. Maximum a posteriori probability. Parallel architecture. Parallel processing. Post-layout simulation. Reduced memory complexity. Symbol-based decoding. Turbo decoder. Turbo equalizer.