Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.
The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential faul...
| Wydane w: | IEEE Transactions on VLSI systems 13, 9 (2005). |
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| Format: | Artykuł |
| Język: | angielski |
| Hasła przedmiotowe: |