Quantitative analysis and optimization techniques for on-chip cache leakage power.

On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In nanometer-scale technology, the subthreshold leakage power is becoming one of the dominant total power consumption components of those caches. In this study, we present optimization technique...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής

Εκδόθηκε σε:	IEEE Transactions on VLSI systems 13, 10 (2005).
Κύριος συγγραφέας:	Nam Sung Kim
Μορφή:	Άρθρο
Γλώσσα:	Αγγλικά
Θέματα:	Cache leakage optimization. Memory access time. Microprocessor core logic. Nanometer-scale technology. On-chip cache leakage power optimization. Subthreshold leakage power reduction.