Microarchitecture-level leakage reduction with data retention.

In this paper, we study microarchitecture-level leakage energy reduction by power gating. We consider the virtual power/ground rails clamp (VRC) and multithreshold CMOS (MTCMOS) techniques and apply VRC to memory-based units for data retention and MTCMOS to the other units. We propose a systematic m...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 11 (2005).
第一著者:	Weiping Liao
フォーマット:	論文
言語:	English
主題:	Adaptive cache decay method. Cache memories. Circuit modeling. Computer architecture. Data retention. Ground rails clamp. Idle period distribution. Memory-based units. Microarchitecture-level leakage energy reduction. Multithreshold CMOS technique. Power gating analysis. Secondary level cache. Very long instruction word processors. Virtual power clamp.