Microarchitecture-level leakage reduction with data retention.

Microarchitecture-level leakage reduction with data retention.

In this paper, we study microarchitecture-level leakage energy reduction by power gating. We consider the virtual power/ground rails clamp (VRC) and multithreshold CMOS (MTCMOS) techniques and apply VRC to memory-based units for data retention and MTCMOS to the other units. We propose a systematic m...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 13, 11 (2005).
Main Author: Weiping Liao
Format: Article
Language:English
Subjects:
Adaptive cache decay method.
Cache memories.
Circuit modeling.
Computer architecture.
Data retention.
Ground rails clamp.
Idle period distribution.
Memory-based units.
Microarchitecture-level leakage energy reduction.
Multithreshold CMOS technique.
Power gating analysis.
Secondary level cache.
Very long instruction word processors.
Virtual power clamp.