Routing architecture optimizations for high-density embedded programmable IP cores.

Programmable logic cores differ from stand-alone field-programmable gate arrays in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing architecture of rectangular programmable logic cores. We quantify the effects of having different X and Y cha...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 11 (2005).
第一著者:	Hallschmid, P.
フォーマット:	論文
言語:	English
主題:	Channel widths. Field-programmable gate arrays. High-density embedded programmable IP cores. Logic block pin placement. Programmable logic devices. Rectangular programmable logic cores. Routing architecture optimization. Switch block.