Routing architecture optimizations for high-density embedded programmable IP cores.

Programmable logic cores differ from stand-alone field-programmable gate arrays in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing architecture of rectangular programmable logic cores. We quantify the effects of having different X and Y cha...

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Bibliographische Detailangaben

Veröffentlicht in:	IEEE Transactions on VLSI systems 13, 11 (2005).
1. Verfasser:	Hallschmid, P.
Format:	Artikel
Sprache:	English
Schlagworte:	Channel widths. Field-programmable gate arrays. High-density embedded programmable IP cores. Logic block pin placement. Programmable logic devices. Rectangular programmable logic cores. Routing architecture optimization. Switch block.