Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 13, 11 (2005).
第一著者: Chatterjee, B.
フォーマット: 論文
言語:English
主題:
1.7 GHz.
180 nm.
32 bit.
CMOS technology.
Arithmetic and log unit.
Automatic test equipment.
Clock frequency.
Delay faults.
Delay-fault testability.
Delay-fault-testable ALU.
Design-for-test scheme.
Digital circuits.
Flip-flops.
Leakage power.
Microprocessor testing.
Very large scale integration.