Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal...

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