Modular and rapid testing of SOCs with unwrapped logic blocks.
Extensive research has been carried out for test planning of core-based system-on-a-chip devices. Most of the prior work assumes that all of the embedded cores are wrapped for test purpose. However, some designs may contain user-defined logic or cores that cannot be wrapped due to area constraints o...
| Publié dans: | IEEE Transactions on VLSI systems 13, 11 (2005). |
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| Format: | Article |
| Langue: | anglais |
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