Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.

We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and tem...

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Xehetasun bibliografikoak

Argitaratua izan da:	IEEE Transactions on VLSI systems 13, 11 (2005).
Egile nagusia:	Kaul, H.
Formatua:	Artikulua
Hizkuntza:	ingelesa
Gaiak:	1 GHz. 130 mm. 9 nm. Bus-invert coding. Dual-rail domino logic. Dynamic bus technique. Energy-delay design space. Low-latency spatial encoder circuits. On-chip buses. Peak current-delay design space. Peak power reduction. Spatial encoding circuits. Static buses. Static input.