Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.

Asynchronous design offers a solution to the interconnect problems faced by system-on-chip (SoC) designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building blo...

पूर्ण विवरण

ग्रंथसूची विवरण
में प्रकाशित:	IEEE Transactions on VLSI systems 13, 12 (2005).
मुख्य लेखक:	Efthymiou, A.
स्वरूप:	लेख
भाषा:	English
विषय:	ATPG. C-element testability. Asynchronous interconnect. Building block. Globally-asynchronous locally-synchronous. Interconnect fabric. Interconnect topology. Level-sensitive scan devices. Network-on-chip. Partial-scan methodology. Scan-testing. Stuck-at fault testing. Synchronous circuit. System-on-chip design. Test pattern generation.