Bus encoding for total power reduction using a leakage-aware buffer configuration.

Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE Transactions on VLSI systems 13, 12 (2005).
1. Verfasser:	Rao, R.R
Format:	Artikel
Sprache:	Englisch
Schlagworte:	Buffer circuit design. Bus encoding. Capacitive crosstalk. Encoding logic complexity. High-threshold voltage transistor. Leakage-aware buffer configuration. On-chip buses. Runtime leakage power. Total power reduction.