Bus encoding for total power reduction using a leakage-aware buffer configuration.

Bus encoding for total power reduction using a leakage-aware buffer configuration.

Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates...

Descrizione completa

Dettagli Bibliografici
Pubblicato in:IEEE Transactions on VLSI systems 13, 12 (2005).
Autore principale: Rao, R.R
Natura: Articolo
Lingua:English
Soggetti:
Buffer circuit design.
Bus encoding.
Capacitive crosstalk.
Encoding logic complexity.
High-threshold voltage transistor.
Leakage-aware buffer configuration.
On-chip buses.
Runtime leakage power.
Total power reduction.