Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications.

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications.

In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-fram...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Transactions on electron devices 50, 1 (2003).
1. autor: Afzalian, A.
Format: Artykuł
Język:English
Hasła przedmiotowe:
0.25 micron.
1.5 V.
2 micron.
3 V.
60.3 dB.
63 dB.
APS imagers.
FPN.
SNR.
SOI CMOS processes.
Si.
Active pixel sensor circuit.
Analytical model.
Bulk CMOS processes.
Fixed pattern noise.
Low-power applications.
Low-voltage applications.
Optimal design.
Performance modeling.
Power consumption.
Thermal noise.
Top-down design.