APA aipamena

Inokawa, H. A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. IEEE Transactions on electron devices.

Chicago Style aipamena

Inokawa, H. "A Multiple-valued Logic and Memory with Combined Single-electron and Metal-oxide-semiconductor Transistors." IEEE Transactions on Electron Devices .

MLA aipamena

Inokawa, H. "A Multiple-valued Logic and Memory with Combined Single-electron and Metal-oxide-semiconductor Transistors." IEEE Transactions on Electron Devices, .