CMOS circuit verification with symbolic switch-level timing simulation.

Symbolic switch-level simulation has been extensively applied to the functional verification of complementary metal-oxide-semiconductor (CMOS) circuitry. We have extended this technique to account for real-valued data-dependent delay values and have developed a novel mechanism for symbolically compu...

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发表在:	IEEE Transactions on computer-aided design of integrated circuits and systems 20, 3 (2001).
主要作者:	McDonald, C.B
格式:	文件
语言:	英语
主题:	CMOS circuit verification. Data-dependent Elmore delays. Delay calculation algorithms. Full-custom transistor-level CMOS circuitry. Real-valued data-dependent delay values. Symbolic switch-level timing simulation.