Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.

Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.

In this paper, we present an algorithm for generating test patterns automatically from functional register-transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. In order to do this, we utilize a data structure named assignment decision diagram that...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on computer-aided design of integrated circuits and systems 20, 3 (2001).
Päätekijä: Ghosh, I.
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
RTL-RTL validation.
RTL-logic validation.
Assignment decision diagrams.
Automatic test pattern generation.
Backtracks.
Data structure.
Design style.
Design turn around time.
Fault coverage.
Functional register-transfer level circuits.
High-level synthesis.
Primitive elements.
Problem size.
Single-clock design.
Stuck-at faults.
Test-generation time.