Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking.

We present a new approach to checking assertion properties for register-transfer level (RTL) design verification. Our approach combines structural word-level automatic test pattern generation (ATPG) and modular arithmetic constraint-solving techniques to solve the constraints imposed by the target a...

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ग्रंथसूची विवरण

में प्रकाशित:	IEEE Transactions on computer-aided design of integrated circuits and systems 20, 3 (2001).
मुख्य लेखक:	Chung-Yang Huan
स्वरूप:	लेख
भाषा:	English
विषय:	ATPG search space. Arithmetic constraint solver. Assertion property checking. Datapath signals. Decision-making process. Implication translation techniques. Industrial designs. Industrial front-end hardware description language. Modular arithmetic constraint-solving techniques. Modular number system. Property-to-constraint converter. Register-transfer level design verification. Target assertion property. Word-level ATPG.