Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking.

We present a new approach to checking assertion properties for register-transfer level (RTL) design verification. Our approach combines structural word-level automatic test pattern generation (ATPG) and modular arithmetic constraint-solving techniques to solve the constraints imposed by the target a...

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Detaylı Bibliyografya
Yayımlandı:IEEE Transactions on computer-aided design of integrated circuits and systems 20, 3 (2001).
Yazar: Chung-Yang Huan
Materyal Türü: Makale
Dil:English
Konular: