Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking.
We present a new approach to checking assertion properties for register-transfer level (RTL) design verification. Our approach combines structural word-level automatic test pattern generation (ATPG) and modular arithmetic constraint-solving techniques to solve the constraints imposed by the target a...
| Yayımlandı: | IEEE Transactions on computer-aided design of integrated circuits and systems 20, 3 (2001). |
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| Materyal Türü: | Makale |
| Dil: | English |
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