Handling the pin overhead problem of DFTs for high-quality and at-speed tests.

The pin overhead problem of nonscan design for testability (DFT) and built-in self-test design has been an unsolved problem for a long time. A new algorithm is proposed to connect extra pins of control test points with primary inputs. An economical test point structure is introduced, in which only o...

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Bibliografische gegevens

Gepubliceerd in:	IEEE Transactions on computer-aided design of integrated circuits and systems 21, 9 (2002).
Hoofdauteur:	Dong Xiang
Formaat:	Artikel
Taal:	English
Onderwerpen:	ATPG. BIST design. Built-in self-test design. Control test points. Delay overhead. Economical test point structure. Inversion parity. Nonscan DFT. Nonscan design for testability. Pin overhead problem. Primary inputs. Reconvergent fanouts. Sequential depth for testability.