Handling the pin overhead problem of DFTs for high-quality and at-speed tests.

Handling the pin overhead problem of DFTs for high-quality and at-speed tests.

The pin overhead problem of nonscan design for testability (DFT) and built-in self-test design has been an unsolved problem for a long time. A new algorithm is proposed to connect extra pins of control test points with primary inputs. An economical test point structure is introduced, in which only o...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on computer-aided design of integrated circuits and systems 21, 9 (2002).
Päätekijä: Dong Xiang
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
ATPG.
BIST design.
Built-in self-test design.
Control test points.
Delay overhead.
Economical test point structure.
Inversion parity.
Nonscan DFT.
Nonscan design for testability.
Pin overhead problem.
Primary inputs.
Reconvergent fanouts.
Sequential depth for testability.