Automatic interconnection rectification for SoC design verification based on the port order fault model.

Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault m...

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書誌詳細

出版年:	IEEE Transactions on computer-aided design of integrated circuits and systems 22, 1 (2003).
第一著者:	Chun-Yao Wang
フォーマット:	論文
言語:	英語
主題:	SoC designs. Automatic interconnection rectification. Combinational benchmarks. Design verification. Embedded cores. Port order fault model. Sequential benchmarks. System-on-a-chip designs.