Timing constraints for domino logic gates with timing-dependent keepers.
Low threshold voltage (Vt) can be applied to domino logic to improve the performance in dual threshold voltage technology. Then, the keeper transistor should be up-sized to compensate for reduced noise margin due to the significant subthreshold current of low Vt transistor. However, a large keeper t...
| Xuất bản năm: | IEEE Transactions on computer-aided design of integrated circuits and systems 22, 1 (2003). |
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| Tác giả chính: | |
| Định dạng: | Bài viết |
| Ngôn ngữ: | Tiếng Anh |
| Những chủ đề: |