Timing constraints for domino logic gates with timing-dependent keepers.

Timing constraints for domino logic gates with timing-dependent keepers.

Low threshold voltage (Vt) can be applied to domino logic to improve the performance in dual threshold voltage technology. Then, the keeper transistor should be up-sized to compensate for reduced noise margin due to the significant subthreshold current of low Vt transistor. However, a large keeper t...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Transactions on computer-aided design of integrated circuits and systems 22, 1 (2003).
Prif Awdur: Seong-Ook Jung
Fformat: Erthygl
Iaith:English
Pynciau:
Circuit optimization.
Contention-free skew-tolerant window.
Delay logic gates.
Design parameter variations.
Domino logic.
Dual keeper structure.
Dual threshold voltage technology.
Evaluation NMOS transistors.
High-speed switching.
Noise margin.
Noise robustness.
Noise tolerance improvement.
Optimal timing conditions.
Signal skew robustness.
Subthreshold current.
Timing analysis.
Tolerance analysis.