Chip-level charged-device modeling and simulation in CMOS integrated circuits.

Chip-level charged-device modeling and simulation in CMOS integrated circuits.

Electrostatic discharge (ESD) accounts for over 30% of chip failure which occurred during chip manufacturing. Inadvertent touching by human body or contact with assembler tray can lead to such ESD failures. The most dominant ESD model is the charged-device model (CDM) wherein energy-destructive fail...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on computer-aided design of integrated circuits and systems 22, 1 (2003).
Päätekijä: Jaesik Lee
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
0.25 micron.
CDM macromodel.
CMOS ASIC.
CMOS ICs.
ESD failures.
Active devices.
Application-specific IC.
Charge-driven behavior.
Charged-device model.
Chip-level charge transfer.
Chip-level charged-device modeling.
Chip-level charged-device simulation.
Chip-level discharge paths.
Chip-level failure mechanisms.
Electrostatic discharge.
Energy-destructive failure.
Failure analysis.
Gate oxide reliability.
Mixed-signal ASIC.
Parasitic elements.
Subsystem boundary.