A CAD methodology for optimizing transistor current and sizing in analog CMOS design.

A CAD methodology for optimizing transistor current and sizing in analog CMOS design.

A computer-aided design (CAD) methodology for optimizing MOS transistor current and sizing is presented where drain current ID, inversion level (represented by inversion coefficient IC), and channel length L are selected as three independent degrees of design freedom resulting in an optimized select...

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Pubblicato in:IEEE Transactions on computer-aided design of integrated circuits and systems 22, 2 (2003).
Autore principale: Binkley, D.M
Natura: Articolo
Lingua:English
Soggetti:
0.5 micron.
DC matching.
MOS inversion coefficient.
MOS transistor.
MOSFET current optimisation.
MOSFET size optimisation.
Analog CMOS design.
Channel length.
Circuit transconductance.
Computer-aided design methodology.
Drain current.
Drain-source saturation voltage.
Flicker noise.
Inversion level.
Optimal DC gain.
Output conductance.
Submicron CMOS process.
Transistor-level CAD methodology.
White noise.