Efficient very large scale integration power

Efficient very large scale integration power

We present an efficient method of minimizing the area of power/ground (P/G) networks in integrated circuit layouts subject to reliability constraints. Instead of directly sizing the original P/G network extracted from a circuit layout, as done previously, the new method first constructs a reduced bu...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003).
1. autor: Tan, S.X.-D
Format: Artykuł
Język:English
Hasła przedmiotowe:
VLSI.
Area minimization.
Circuit optimization.
Circuit reliability.
Equivalent circuit model.
Integrated circuit layout.
Power distribution.
Power/ground network sizing algorithm.
Sequence of linear programming method.