Efficient very large scale integration power
We present an efficient method of minimizing the area of power/ground (P/G) networks in integrated circuit layouts subject to reliability constraints. Instead of directly sizing the original P/G network extracted from a circuit layout, as done previously, the new method first constructs a reduced bu...
| 發表在: | IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003). |
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| 格式: | Article |
| 語言: | English |
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