Efficient very large scale integration power

Efficient very large scale integration power

We present an efficient method of minimizing the area of power/ground (P/G) networks in integrated circuit layouts subject to reliability constraints. Instead of directly sizing the original P/G network extracted from a circuit layout, as done previously, the new method first constructs a reduced bu...

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Bibliographic Details
Published in:IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003).
Main Author: Tan, S.X.-D
Format: Article
Language:English
Subjects:
VLSI.
Area minimization.
Circuit optimization.
Circuit reliability.
Equivalent circuit model.
Integrated circuit layout.
Power distribution.
Power/ground network sizing algorithm.
Sequence of linear programming method.