Minimum buffered routing with bounded capacitive load for slew rate and reliability control.
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise. Bounding load capacitance also improves reliability with...
| Published in: | IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003). |
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| Main Author: | |
| Format: | Article |
| Language: | English |
| Subjects: |