High-speed operation of a low-power 4-bit serial-to-parallel converter.

High-speed operation of a low-power 4-bit serial-to-parallel converter.

This paper presents a high-speed low-power 4-bit superconducting serial-to-parallel converter (SPC) that has been demonstrated experimentally to operate at data rates up to 1 Giga-bits (Gb/s). The primary design goals for this device are high-speed operation, low-power dissipation, and high circuit...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on applied superconductivity 12, 4 (2002).
Päätekijä: Vichot, P.A
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
1 Gbit/s.
100 Mbit/s.
20 Gbit/s.
28 muW.
4 bit.
Address decoder.
Circuit design.
Circuit optimization.
Continuous operation.
Core element.
Data rate.
Demultiplexer.
Design goals.
High circuit yield.
High-speed operation.
Latching logic.
Low-power 4-bit superconducting serial-to-parallel converter.
Power dissipation.
Simulated circuit performance.
Within-wafer yield.