Calibrating simulation tools for nanometer designs.

Next-generation silicon processes will challenge system-on-a-chip (SOC) designers to increase the accuracy of the data they feed to their high level tools. Minimum circuit features of 250 nm (0.25 μm) or below are demanding. The tools that simulate them will need transistor models and interconnect p...

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Publicat a:	IEEE spectrum 36, 6 (1999).
Autor principal:	Shahram, M.
Format:	Article
Idioma:	English
Matèries:	Electronic design automation. Interconnect parameters. Nanometer circuit design. Next-generation silicon processes. Silicon-calibrated models. Simulation tools calibration. System-on-a-chip design. Transistor models. Transistor-level simulation tools.