An 8.1-ns Column-Access 1.6-Gb/s 4 Multiplexed Data-Transfer Scheme.

Three circuit techniques for an 8.1-ns column-access 1.6-Gb/s/pin 512-Mb DDR3 SDRAM using 90-nm dual-gate CMOS technology were developed. First, an 8:4 multiplexed data-transfer scheme, which operates in a quasi-4-bit prefetch mode, achieves a 3.17-ns reduction in column-access time, i.e., from 11.3...

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Bibliographic Details
Published in:	IEEE Journal of solid state circuits 42, 1 (2007).
Main Author:	Fujisawa, H.
Format:	Article
Language:	English
Subjects:	1.2 ns. 1.36 V. 1.6 Gbits/s. 120 ohm. 20 ohm. 30 ohm. 40 ohm. 60 ohm. 8.13 ns. 90 nm. DDR3 SDRAM. ZQ calibration. Data-transfer scheme. Dual-clock latency counter. Dual-gate CMOS technology.