An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I

This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 M...

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Publicat a:	IEEE Journal of solid state circuits 42, 1 (2007).
Autor principal:	Kim, K.-h
Format:	Article
Idioma:	English
Matèries:	10 bit. 288 MByte. 8 Gbit/s. 9.6 ns. I/O error detection scheme. SDRAM. Deca-data rate clocking scheme. Memory interface. Multiphase clock generation.