A 125 μW , Fully Scalable MPEG-2 and H.264

A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to red...

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書目詳細資料
發表在:	IEEE Journal of solid state circuits 42, 1 (2007).
主要作者:	Liu, T.-M
格式:	Article
語言:	English
主題:	0.18 micron. 1 V. 1.15 MHz. 108 muW. 125 muW. CMOS technology. H.264/AVC BL@L4. MPEG-2 SP@ML. Bandwidth scalability. Deblocking filter. Domain-pipelined scalability. Internal memory size reduction. Inverse discrete cosine transform. Line-pixel-lookahead scheme. Low-power motion compensation. Memory power reduction. Mobile communication. Pipelined structure. Power dissipation. Quarter-common intermediate format sequences. Video coding. Video decoding.