Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power...

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Manylion Llyfryddiaeth

Cyhoeddwyd yn:	IEEE Journal of solid state circuits 42, 1 (2007).
Prif Awdur:	Kanno, Y.
Fformat:	Erthygl
Iaith:	Saesneg
Pynciau:	90 nm. Clock gating. Hierarchical power distribution. Leakage currents. Low power multiCPU SoC. Power gating. Power tree management rules. Power tree structure.