A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm2 die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction m...

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Bibliographic Details
Published in:IEEE Journal of solid state circuits 42, 1 (2007).
Main Author: Rusu, S.
Format: Article
Language:English
Subjects:
1 MByte.
16 MByte.
65 nm.
L3 cache.
Circuit design.
Control logic.
Dual-core multithreaded Xeonreg processor.
Leakage reduction.
Long channel transistors.
Unified L2 cache.