A 22-gb

We report a receiver for four-level pulse-amplitude modulated (PAM-4) encoded data signals, which was measured to receive data at 22 Gb/s with a bit error rate (BER) <10-12 at a maximum frequency deviation of 350 ppm and a 27-1 PRBS pattern. We propose a bit-sliced architecture for the data path,...

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Xehetasun bibliografikoak
Argitaratua izan da:	IEEE Journal of solid state circuits 41, 4 (2006).
Egile nagusia:	Toifl, T.
Formatua:	Artikulua
Hizkuntza:	English
Gaiak:	1.1 V. 207 mA. 22 Gbit/s. 90 nm. 90nm CMOS SOI technology. CML biasing scheme. PAM-4 receiver. PRBS pattern. Analog equalizer. Bit error rate. Bit-sliced architecture. Current consumption. Current-mode logic biasing scheme. Differential data signal. Encoded data signals. Offset compensation. Programmable matched resistors. Programmable offset. Programmable signal termination. Pulse-amplitude modulation. Sampling latches. Voltage shifting amplifier.