A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A
A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-μm CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the o...
| Published in: | IEEE Journal of solid state circuits 41, 4 (2006). |
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| Main Author: | |
| Format: | Article |
| Language: | English |
| Subjects: |