A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A

A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-μm CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the o...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Journal of solid state circuits 41, 4 (2006).
1. autor: Varzaghani, A.
Format: Artykuł
Język:English
Hasła przedmiotowe:
0.18 micron.
1.5 bit.
1.8 V.
170 fF.
3 GHz.
4 bit.
6 bit.
780 mW.
CMOS technology.
DFE tap coefficient.
ISI subtraction.
Analog-digital converter.
Channel equalization.
Code-overlapping.
Digital error correction.
Feedback delay requirement.
Low-frequency input SNDR.
Multilevel decision feedback equalizer.
Pipeline A/D converter.
Serial-link receiver.