A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment tem...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Journal of solid state circuits 41, 4 (2006).
Prif Awdur: Iizuka, K.
Fformat: Erthygl
Iaith:English
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