A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC.

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage ΔΣ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q2 Random Walk switching scheme. The ΔΣ interpolator is used to reduce the phase truncation e...

詳細記述

書誌詳細
出版年:	IEEE Journal of solid state circuits 41, 4 (2006).
第一著者:	Fa Foster Dai
フォーマット:	論文
言語:	English
主題:	0.35 micron. 12 bit. 16 bit. 200 mW. 3.3 V. 8 bit. CMOS technology. DDFS prototype. ROM size. Current-steering DAC. Delta-sigma noise shaper. Direct digital frequency synthesizer. Fourth-order phase domain noise shaper. Phase truncation error. Random walk switching scheme. Single-stage delta-sigma interpolator. Spurious-free dynamic range.