A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques.

A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques.

A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and CIO minimization, which were achieved by on-die-termination (ODT)-merged output drivers,...

תיאור מלא

מידע ביבליוגרפי
הוצא לאור ב:IEEE Journal of solid state circuits 41, 4 (2006).
מחבר ראשי: Churoo Park
פורמט: Article
שפה:English
נושאים:
1.5 V.
512 Mbit.
80 nm.
DDR3 SDRAM prototype.
DDR3 point-to-2points interfacing.
DDR3 synchronous DRAM prototype.
SCR type ESD protection.
Double data rate SDRAM.
Hybrid latency control scheme.
On-chip sensor.
On-die-termination.
Per-bank-refresh.
Self-calibration techniques.
Signal integrity.
Temperature read-out.
CIO minimization.