Churoo Park. A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. IEEE Journal of solid state circuits.
Citace podle Chicago (17th ed.)Churoo Park. "A 512-mb DDR3 SDRAM Prototype with CIO Minimization and Self-calibration Techniques." IEEE Journal of Solid State Circuits .
Citace podle MLA (9th ed.)Churoo Park. "A 512-mb DDR3 SDRAM Prototype with CIO Minimization and Self-calibration Techniques." IEEE Journal of Solid State Circuits, .
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