An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology.

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology.

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monit...

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Bibliographic Details
Published in:IEEE Journal of solid state circuits 41, 4 (2006).
Main Author: Sohn, K.
Format: Article
Language:English
Subjects:
512 kbit.
80 nm.
SRAM chip.
Autonomous SRAM.
Double stacked cell technology.
Internal supply voltage.
Internal timing margin.
Leakage current monitor.
Nanotechnology SRAM.
On-chip sensors.
On-chip timer.
Substrate noise detector.
Temperature sensor.