Buchumschlag

A high-speed and low-voltage associative co-processor with exact Hamming

A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten...

Ausführliche Beschreibung

Bibliographische Detailangaben
Veröffentlicht in:IEEE Journal of solid state circuits 39, 8 (2004).
1. Verfasser: Oike, Y.
Format: Artikel
Sprache:Englisch
Schlagworte:
0.18 micron.
0.75 V.
1 V.
1.8 V.
32-word database.
40.0 MHz.
411.5 MHz.
64 bit.
Hamming distance estimation.
Manhattan distance estimation.
Bit-serial search architecture.
Capacity scalability.
Clocks.
Content addressable memory.
Hierarchical architecture.
Hierarchical search architecture.
High-speed operation.
Logic-in-memory architecture.
Logic-in-memory digital implementation.
Low-voltage associative co-processor.
Low-voltage operation.
Nearest-match detection.
One-poly-Si five-metal CMOS process.
Search cycle time.
System-on-a-chip applications.
Thermometer encoding.
Unlimited database capacity.
Word-parallel search architecture.