Techniques for phase noise suppression in recirculating DLLs.
This paper presents two techniques for reducing phase noise in recirculating delay-locked loops (DLLs) and extends recently developed theoretical results to optimize the performance of a recirculating DLL prototype CMOS IC incorporating the techniques. One of the techniques reduces 1/f noise in both...
| প্রকাশিত: | IEEE Journal of solid state circuits 39, 8 (2004). |
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| প্রধান লেখক: | |
| বিন্যাস: | প্রবন্ধ |
| ভাষা: | English |
| বিষয়গুলি: |