Power optimized partial scan BIST implementation on DLX microprocessor
The need for efficient chip testing methods is needed as integrated circuits become more complex. Together with this is the increase in costs in terms of time and monetary resources with the use of external Automated Test Equipment (ATEs). One alternative is the incorporation of a Built-in Self-test...
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| その他の著者: | , |
| フォーマット: | 学位論文 |
| 言語: | English |
| 出版事項: |
2010
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