A 0.5-V 1-μW successive approximation ADC.

A 0.5-V 1-μW successive approximation ADC.

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-μm standard CMOS technology. Neither low-VT devices nor voltage boosting techniques are used. All voltage levels are between supply voltage VDD and groun...

詳細記述

書誌詳細
出版年:IEEE Journal of solid state circuits 38, 7 (2003).
第一著者: Sauerbrey, J.
フォーマット: 論文
言語:English
主題:
0.18 micron.
0.5 V.
1 muW.
CMOS technology.
Capacitor-based digital-to-analog converter.
Passive sample-and-hold stage.
Power consumption.
Sampling rate.
Signal-to-noise-and-distortion ratio.
Successive approximation analog-to-digital converter.
Ultralow voltage operation.